The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit including a power supply voltage controller which limits the change rate when the power supply voltage is to be changed.
Recently, to reduce the power consumption of a semiconductor integrated circuit, the power supply voltage is dropped to a minimum necessary voltage in accordance with the operation state.
For example, a 100-MHz, 1.2-V semiconductor integrated circuit is sometimes operated by downing the power to 50 MHz and 0.9 V in accordance with the margin of the data processability. In this case, before the power supply voltages are switched, the clock is lowered from 100 MHz to 50 MHz to temporarily stop data processing. Then, the power supply voltage is lowered from 1.2 V to 0.9 V, and data processing is resumed after the voltage has stabilized.
To return to 100 MHz and 1.2 V, data processing is temporarily stopped before the power supply voltages are switched. After the power supply voltage is raised from 0.9 V to 1.2 V and the voltage has stabilized, the clock is returned from 50 MHz to 100 MHz to resume data processing.
This is so because, during the abrupt transition of the power supply voltage, a problem such as clock out of sync or circuit delay fluctuation arises, and it is necessary to avoid a period like this.
It is also necessary to avoid the problem that a period during which the power supply voltage falls outside the operating voltage is produced by overshoot caused by an abrupt transition of the power supply voltage. That is, it is necessary to avoid the event in which, assuming that the designed voltages are 1.2 V±0.05 V and 0.9 V±0.05 V, no stable operation can be ensured any longer because these voltage ranges are exceeded.
Conventionally, therefore, before and after the power supply voltages are switched, data processing must be temporarily stopped until the power supply voltage stabilizes, and this lowers the processing speed.
A reference disclosing the conventional semiconductor integrated circuit is as follows.
Japanese Patent Laid-Open No. 2003-330549